Optimization of the Two-Level Mealy Machine Circuit in the FPGA Basis
DOI:
https://doi.org/10.15407/intechsys.2025.01.024Keywords:
Mealy FSM, synthesis, FPGA, EMB, LUT, state coding, input replacementAbstract
Introduction. One of the most important parts of any digital system is a control unit (CU), which coordinates the interaction of other blocks of the system. As a rule, the CU circuit is determined by the control algorithm, and the design of each CU starts from scratch due to the uniqueness of its operating algorithm.
The purpose of the paper is The quality of a digital system depends on the optimality of the CU characteristics. Therefore, the development of effective methods for optimizing CU circuits is so important. When synthesizing a CU circuit, a number of optimization problems arise: reducing the chip area occupied by the CU, increasing the performance reducing the power consumption. It is known that solving the first of these problems allows improving other characteristics of the circuit. This paper considers the problem of reducing the chip area when implementing the CU circuit using FPGA (field-programmable logic array) chips.
Methods. The FPGA chips and the Mealy finite state machine (FSM) model are selected as the objects of study in the article. When implementing the FSM circuit with FPGAs, LUT (look-up table) elements and embedded memory blocks (EMB) are used. Since the dominant manufacturer of FPGA chips is AMD Xilinx, the method proposed in the article is oriented towards FPGA of this company.
The article proposes a method for reducing hardware costs when implementing the Mealy FSM circuit in the FPGA basis. The method is based on the joint use of the EMB embedded memory blocks and LUT elements. The limiting case is considered when the developer can use only one EMB block. To optimize the circuit, the methods of replacing the FSM inputs and double state coding are used. An example of applying the proposed method is given.
Results. The proposed method allows reducing the number of LUT elements used by up to 18%. The conditions for the feasibility of using the method are shown.
Conclusions. It makes sense to modify the proposed method for the case of Moore FSMs.
References
Marwedel P. Embedded System Design: Embedded Systems Foundations of Cyber-Physical Systems, and the Internet of Things. Springer International Publishing, 3rd ed., 2018.
Minns P., Elliot I. FSM-based digital design using Verilog HDL. John Wiley and Sons, 2008. https://doi.org/10.1002/9780470987629
Baranov S. Finite State Machines and Algorithmic State Machines. Amazon, 2018.
Barkalov A., Titarenko L., Mielcarek K., Chmielewski S. Logic Synthesis for FPGA-Based Control Units — Structural Decomposition in Logic Design. Lecture Notes in Electrical Engineering, Springer, Berlin, 2020, Vol. 636. https://doi.org/10.1007/978-3-030-38295-7
Gazi O., Arli A. State Machines using VHDL: FPGA Implementation of Serial Communication and Display Protocols. Springer, Berlin, 2021. https://doi.org/10.1007/978-3-030-61698-4
De Micheli G. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.
Trimberg S. Three ages of FPGA: A retrospective on the first thirty years of FPG Atechnology. IEEE Proceedings, 2015, Vol. 103 (3), 318–331. https://doi.org/10.1109/JPROC.2015.2392104
Wolf W. FPGA-Based System Design. Prentice Hall PTR, Upper Saddle River, New Jersey, USA, 2004.
Ruiz-Rosero, Juan, Gustavo Ramirez-Gonzalez, Rahul Khanna. Field Programmable Gate Array Applications—A Scientometric Review. Computation 7, 2019, Vol. 4, 63 p. https://doi.org/10.3390/computation7040063
Maxfield C. FPGAs: Instant access. Newnes, 2008.
Xilinx. URL: https://www.amd.com/en.html [Accessed Jan. 2025]
Garcia-Vargas I., Senhadji-Navarro R., Jimnez-Moreno G., Civit-Balcells A., GuerraGutierrezz P. ROM-based finite state machines implementation in low cost FPGAs. IEEE Intern. Simp. on Industrial Electronics (ISIE’07) (Vigo, 2007), 2007, 2342–2347. https://doi.org/10.1109/ISIE.2007.4374972
Garcia-Vargas L., Senhaji-Navarro R. Finite state machines with input multiplexing: A performance study. IEEE Transactions on CAD of Integrated Circuits and Systems, 2015, Vol. 34 (5), 867–871. https://doi.org/10.1109/TCAD.2015.2406859
Sklyarov V., Skliarova I., Barkalov A., Titarenko L. Synthesis and optimization of FPGA-based systems. Berlin: Springer, 2014, 432 p. https://doi.org/10.1007/978-3-319-04708-9
Virtex-7 FPGAs. URL: https://docs.amd.com/v/u/en-US/7-series-product-selectionguide [Accessed Jan. 2025]
Czerwinski R., Kania D. Finite state machines logic synthesis for complex pro gra mmable logic devices. Berlin: Springer, 2013, 172 p. https://doi.org/10.1007/978-3-642-36166-1
Tiwari A., Tomko K. Saving power by mapping finite state machines into em bedded memory blocks in FPGAs. Proc. Design, Automation and Test in Europe Conference and Exhibition (Paris, France, 6-20 Feb. 2004), 2004, Vol. 2, 916–921. https://doi.org/10.1109/DATE.2004.1269007
Yang S. Logic synthesis and optimization benchmarks user guide. Version 3.0. Techn. Rep. Microelectronics Center of North Carolina, 1991, 43 p.
Vivado. URL: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html [Accessed Jan. 2025]
Barkalov A. and Titarenko L. Logic synthesis for FSM-based control units. Lecture notes in electrical engineering, Springer-Verlag, Berlin, 2009, Vol. 53. https://doi.org/10.1007/978-3-642-04309-3_3
Barkalov A., Titarenko L., Kolopienczyk M., Mielcarek K., Bazydlo G. Logic synthesis for FPGA-based Finite State Machines. Studies in Systems, Decision and Control, Springer International Publishing, Cham Heidelberg, 2015, Vol. 38, 280 p. https://doi.org/10.1007/978-3-319-24202-6
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