New Method for Generating Test Codes to Detect Multiple Stuck-at-Faults in Combinational Circuits. Part 1
DOI:
https://doi.org/10.15407/intechsys.2025.02.034Keywords:
combinational circuit, single and multiple stuck-at-faults (0/1) type damage, q-partition of minterms, nonessential variables, vector of test codesAbstract
The article is devoted to a new method of generating test codes to detect multiple damages in digital combinational circuits, which is based on the artificial introduction of nonessential variables and the application of the procedure of q-partition of minterms of a given function. Due to the use of a numerical set-theoretic approach, the proposed method differs from the known ones in a relatively simpler practical implementation to detect stuck-at-faults (0/1) type both at one point and at several points simultaneously of the circuit under study.
References
Rytsar B. Ye. A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits. Control Systems and Computers, 2023, Vol. 1 (301), 5–17. https://doi.org/10.15407/csc.2023.01.005
Rytsar B. Ye. A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits. II. Control Systems and Computers, 2024, Vol. 1 (301), 3–17. https://doi.org/10.15407/csc.2024.01.003
Azam Beg. A framework for finding minimal test vectors for stuck-at-faults. 3rd Inter. Conf. ICICT’2009 – Aug 2009,Karachi, Pakistan, 259–262.
Jong Chang Kim, Vishvani D. Agraval, Kewal K. Saluja. Multiple Faults: Modeling, Simulation and Test. 7th ASPDAC and 15th Int’l Conf. on VLSI Design, 2002, pp. 592–597.
Jutman A., Ubar R. Design error diagnostic in digital circuits with stuck-at-fault model. Microelectronics Reliability, 28 Febr. 2000, Vol. 40 (2), 307–320.
Koundinya P., Reddy S., Deepak V., Rutwesh K., Deshpande A.. Test Set Generation for Multiple Faults in Boolean Systems using SAT Solver. 12th Inter. Conf. ICCCNT – 06-08 July 2021, 329–340.
Parag K. Lala. An Introduction to Logic Circuit Testing. Morgan & Claypool, 2009, 111 p.
Kohavi Z., Jha N. Switching and Finite Automata Theory. Cambridge University Press, 2010, 206—250.
Leila Malihi, Razieh Malihi. Single stuck-at-faults detection using test generation vector and deep stacked-sparse-auto-encoder. SN Applied Sciences, 2020, Vol. 2 (1715). https://doi.org/10.1007/s42452-020-03460-0
Fujiwara H. Logic testing and design for testability. In Comp. Syst. Series. Cambridge, MA: Mass. Inst. Tech, 1986.
Karkouri Y, Aboulhamid. Multiple Stuck-at Fault in Logic Circuits. URL: http://www.iro.umontreal.ca/~aboulham/pdfs_sources/KCCVLSI.pdf
Rytsar B.Ye. Dekompozytsija bulovykh funktsij metodom q-rozbyttja. UsiM, 1999, Issue 6, 29–42. [In Ukrainian: Рицар Б.Є. Декомпозиція булових функцій методом q-розбиття. 1]
Rytsar B.Ye. Teoretyko-mnozhynni optymizatsijni metody lohikovoho syntezu kombinatsijnykh merezh. Dissertation DSc (Engineering), Lviv, 2004, 138–142. [In Ukrainian: Рицар Б.Є. Теоретико-множинні оптимізаційні методи логікового синтезу комбінаційних мереж: дис. доктора техн.наук. Львів, 2004,138–142.]
Rytsar B., Romanowski P., Shvay A. Set-theoretical Constructions of Boolean Functions and theirs Applications in Logic Synthesis. Fundamental Informatica, 2010, Vol. 99, №3, 339–354.
Downloads
Published
How to Cite
Issue
Section
License
Copyright (c) 2025 Information Technologies and Systems

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
The paper is an Open Access under the CC BY-NC-ND 4.0 license - Attribution-NonCommercial-NoDerivatives 4.0 International.