Synthesis of a Compositional Microprogram Control Unit with Two Cores of Partial Functions
DOI:
https://doi.org/10.15407/intechsys.2026.03.015Keywords:
partial function, kernel, CMCU, LUT, EMB, synthesys, structural decompositionAbstract
Introduction. Digital systems consist of combinational and sequential blocks. The most important sequential blocks include control units (CU). The circuits of CUs are not standard library components in CAD systems, so designing a particular CU circuit is a more labor-intensive process than implementing systems from common blocks such as registers, counters, arithmetic blocks, and logic blocks.
The quality of a digital system depends on the optimal characteristics of the CU. When synthesizing a CU circuit, it is necessary to solve a number of optimization problems: reducing the chip area occupied by the CU, increasing performance, and reducing power consumption. It is believed that solving the first of these problems allows improving other characteristics of the CU circuit.
Purpose of the work. The main focus of this article is the development of effective methods for optimizing the parameters of CU circuits when implemented on an FPGA (field-programmable gate array) basis.
Methods. A method for structural decomposition of a Compositional Microprogram Control Unit (CMCU) circuit in an FPGA is proposed. The method is based on the identification of two cores of partial functions. One core is based on the functional decomposition and generates functions for which the number of arguments exceeds the number of LUT inputs. The second core is based on the adaptation of twofold state assignments methods to the specifics of CMCU. This core generates functions based on the encoding of operator linear chains.
Results. An CMCU architecture with two cores of partial functions and a method for synthesizing the CMCU circuit are proposed. The FPGA implementation of the CMCU circuit used look-up tables (LUTs) and embedded memory blocks (EMBs). Since AMD Xilinx is the dominant FPGA chip manufacturer, the method proposed in this article is tailored to FPGAs from this company.
An example of synthesizing a CMCU circuit with two cores is presented. The conditions for applying this approach are discussed. Possible solutions to optimization problems associated with imbalances in the characteristics of the control algorithm and LUT elements are demonstrated.
Conclusion. During the synthesis of a CMCU with two cores of partial functions, a number of optimization problems arise. This is necessitated by an imbalance between: 1) the number of classes in the operator linear chains set partitioning and the number of LUT element inputs, and 2) the number of address variables and the number of LUT element inputs. This article analyzes these situations and identifies the corresponding conditions. In our future research, we intend to develop a method for mitigating the impact of these factors.
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